Design Flow with LPM

LPM fits into any standard design flow used for designing PLDs, Gate Arrays, or Standard Cells. The library works equally well with HDLs (Verilog HDL or VHDL), schematics, or block diagrams, and can be used during functional or pre-route simulation.

Figure 1 shows how LPM fits into a standard design flow while providing technology-independent design entry. Each EDA supplier will provide the symbol and functional library. For the technology mapping phase, each technology vendor will provide a file that contains optimized implementations of each LPM function. These optimized functions can be used to by any EDA vendor to map to any technology.

Figure 1. The typical design flow using LPM.

When designing with schematics or block diagrams, the LPM symbols replace the use of tool- or technology-specific symbols. The LPM symbols have the advantage of being scalable and easier to understand. Once the schematic is entered, functional simulation can be completed within any standard simulator. The output netlist from the schematic contains LPM symbols and can be passed on to technology mapping and place and route. From this point on, the design becomes technology specific.

When designing with HDLs, the designer may decide to instantiate LPM functions within the source. It is easier, for example, to instantiate an LPM-style counter than it is to specify the functionality with behavioral code. These instantiated functions are passed directly into the output netlist while the rest of the design is mapped to the target technology.

In addition to the instantiated LPM functions, sophisticated logic synthesis programs can infer LPM functions from the behavioral description. For example, a synthesis tool may choose to map all "+" operators within the HDL file to an LPM_ADD_SUB function with the appropriate parameters to create addition. By inferring an LPM adder from the behavioral description, the EDA tool frees designer to use behavioral code without sacrificing silicon efficiency.

Whether schematics or HDLs are used as design entry, eventually a netlist containing the LPM functions is passed on to the technology-specific fitter for final placement and routing. The fitter will output the appropriate object files to implement the design, along with netlists containing the post-route timing of the design.