| Single Process VHDL Synthesis Examples | |||||||
|---|---|---|---|---|---|---|---|
| Synthesis Template | source | object | |||||
| Register Stack | source | object | |||||
| Rising Level Counter | source | object | |||||
| Clk Enabled Counters | source | object | map | ||||
| Reference Design | source | object | testbench | log | waves |
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| Examples have been used successfully on Quartus, ISE, Leonardo, Synplify, Modelsim, and NC-Sim. Examples are not compatible with Synopsys tools. Reports for other tools are appreciated. | |||||||
| VHDL Language Examples | ||||
|---|---|---|---|---|
| Bi-Directional Port | source | waves | ||
| Remote Testbench Procedure | source | |||
| Block RAM FIFO | source | |||
| Read, Write Binary File | source | |||
| ROM | source | |||
| Functions: int2sgn, vec_image, power2. | source | |||
