System16 - 16 bit CPU Opcode Map
Basic Instruction Format:
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Dual Operands
Target Register (Rt)
Size
EA Mode
EA Register (Rea)
Single Operand
Instruction Type
Size
EA Mode
EA Register (Rea)
Single Operand
Inherent Instruction
Instruction Type
EA Register (Rea)
Bit / Shift Instructions
Target Register (Rt)
S/D
Instruction Type
Control Reg (Rea)
Branch Conditional
Condition Code
Displacement ( 0 -> post byte offset)
(B15:B12) = Dual Operand Opcode Field
(B11:B8) = Target Register (Rt)
(B7) = Size
(B6:B4) = Effective Addressing Mode
(B3:B0) = Effective Address Register (Rea)
0
0
0
0
Single Operand Instructions
0
0
0
1 Bit / Shift Instructions
0
0
1
0
Branch Conditional (Bcc)
0
0
1
1
EOR Rt,EA
0
1
0
0
AND Rt,EA
0
1
0
1
OR Rt,EA
0
1
1
0
ADD Rt,EA
0
1
1
1
SUB Rt,EA
1
0
0
0
ADC Rt,EA
1
0
0
1
SBC Rt,EA
1
0
1
0
BIT Rt,EA
1
0
1
1
CMP Rt,EA
1
1
0
0
LD Rt,EA
1
1
0
1
ST Rt, EA
1
1
1
0
MUL Rt,EA
1
1
1
1
LEA Rt,EA
(B15:B12) = 0000 = Single Operand Instructions
(B11:B8) = Instruction Type
(B7) = Size
(B6:B4) = Effective Addressing Mode
(B3:B0) = Effective Address Register (Rea)
0
0
0
0
Inherent Instruction
0
0
0
1
Decimal Adjust DAA EA
0
0
1
0
Negate NEG EA
0
0
1
1 Complement COM EA
0
1
0
0
Logical Shift Right LSR EA
0
1
0
1
Swap Byte Order SWP EA
0
1
1
0
Rot thru Carry Right RCR EA
0
1
1
1
Arith Shift Right ASR EA
1
0
0
0
Arith Shift Left ASL/LSL EA
1
0
0
1
Rot thru Carry Left RCL EA
1
0
1
0
Decrement DEC EA
1
0
1
1 Jump to Subroutine JSR EA
1
1
0
0
Increment INC EA
1
1
0
1
Test TST EA
1
1
1
0
Jump JMP EA
1
1
1
1
Clear CLR EA
(B15:B12) = 0001 = Bit / Shift Instructions
(B11:B8) = Target Register (Rt)
(B7) = Static / Dynamic
(B6:B4) = Instruction Type
(B3:B0) = Control Register (Rea)
0
0
0
0
Static Bit Test BTST #n,Rt
0
0
0
1
Static Bit Chg BCHG #n,Rt
0
0
1
0
Static Bit Set BSET #n,Rt
0
0
1
1
Static Bit Clear BCLR #n,Rt
0
1
0
0
Static Shift Left SHL #n,Rt
0
1
0
1
Static Shift Right SHR #n,Rt
0
1
1
0
Static Rot Left ROL #n,Rt
0
1
1
1 Static Rot Right ROR #n,Rt
1
0
0
0
Dyn Bit Test BTST Rea,Rt
1
0
0
1
Dyn Bit Chg BCHG Rea,Rt
1
0
1
0
Dyn Bit Set BSET Rea,Rt
1
0
1
1
Dyn Bit Clear BCLR Rea,Rt
1
1
0
0
Dyn Shift Left SHL Rea,Rt
1
1
0
1
Dyn Shift Right SHR Rea,Rt
1
1
1
0
Dyn Rot Left ROL Rea,Rt
1
1
1
1
Dyn Rot Right ROR Rea,Rt
(B15:B12) = 0010 = Branch on Condition Code
(B11:B8) = Condition Code
(B7:B0) = Displacement
0
0
0
0
Always BRA
0
0
0
1
Never BRN
0
0
1
0
Higer BHI
0
0
1
1
Low or Same BLS
0
1
0
0
Carry Clear BCC/BHS
0
1
0
1
Carry Set BCS/BLO
0
1
1
0
Not Equal BNE
0
1
1
1
Equal BEQ
1
0
0
0
Overflow Clear BVC
1
0
0
1
Overflow Set BVS
1
0
1
0
Positive(Plus) BPL
1
0
1
1
Negative(Minus) BMI
1
1
0
0
Greater or Equal BGE
1
1
0
1
Less Than BLT
1
1
1
0
Greater Than BGT
1
1
1
1
Less or Equal BLE
(B15:B12) = 0000 = Single Operand
(B11:B8) = 0000 = Inherent Instruction
(B7:B4) = Instruction Type
(B3:B0) = Effective Address Register (Rea)
0
0
0
0
No Operation NOP
0
0
0
1
*
0
0
1
0
Pull PUL Rea
0
0
1
1 Push PSH Rea
0
1
0
0 Software Interrupt SWI #vec
0
1
0
1
Wait for Interrupt WAI
0
1
1
0 Return From Subroutine RTS
0
1
1
1
Return from Interrupt RTI
1
0
0
0
Load Cond Code LCC Rea
1
0
0
1 Store Cond Code SCC Rea
1
0
1
0
And Cond Code ACC Rea
1
0
1
1 Or Cond Code OCC Rea
1
1
0
0 Load Int Mask LIM Rea
1
1
0
1
Store Int Mask SIM Rea
1
1
1
0
And Int Mask AIM Rea
1
1
1
1
Or Int Mask OIM Rea
Word Size (B7)
0
8 Bit Byte (OP.B)
1
16 Bit Word (OP.W)
EA Addressing Modes (B6:B4):
EA Register = 0000 to 1101
0
0
0
Constant (0-13)
0
0
1
Register Rea
0
1
0
Indexed Auto Increment (Rea)+
0
1
1
Decrement Auto Indexed -(Rea)
1
0
0
Indexed (Rea)
1
0
1
Indexed PC Rel: (Rea,PC)
1
1
0
Indexed Offset disp(Rea)
1
1
1
Indexed Offset Rel disp(Rea,PC)
EA Register = 1110 to 1111
0
0
0 Constant (14 - 15)
0
0
1
Immediate #value
0
1
0
*
0
1
1
*
1
0
0 Absolute: address
1
0
1
PC Relative: disp(PC)
1
1
0
Absolute Indirect: (address)
1
1
1
PC Relative Indirect: (disp(PC))