1.1.8 Mealy Example

architecture RTL of MEDVEDEV_TEST is
    signal STATE,NEXTSTATE : STATE_TYPE ;
begin
    REG: process (CLK, RESET) begin
       if RESET=`1` then
          STATE <= START ;
       elsif CLK`event and CLK=`1` then
          STATE <= NEXTSTATE ;
       end if ;
    end process REG;

    CMB: process (A,B,STATE) begin
       -- Like Medvedev and Moore Examples
    end process CMB ;

    -- concurrent signal assignments for output
    Y <= `1` when (STATE=MIDDLE and (A or B)=`0`)
               or (STATE=STOP and (A and B)=`0`)
             else `0` ;

    Z <= `1` when (STATE=START and (A and B)=`1`)
               or (STATE=MIDDLE)
               or (STATE=STOP and (A or B)=`1`)
             else `0` ;

end RTL ;