Implementation of 8051 Microcontroller Core in Xilinx FPGA

8051 Microcontroller Core
  • The 8051 microcontroller core is useful for SOC (System On Chip) design.
  • The core is originated from Dalton Project, Department of Computer Science, University of California.
  • Limitations applied to the original design is also applied here, where peripherals including interrupts, timers, and UART are not implemented in the core.
  • The core is purely written in VHDL. Thus, it's customizable for designer's needs.
  • Several parts of the core has been modified to optimize for implementation in Xilinx FPGA, particularly, Spartan and Virtex families having Block RAM feature.
  • Modified components include:
  • Internal RAM: Use RAM16X1S primitive instead of flip-flops, saving many CLBs.
  • Program ROM: Use Block RAM as ROM with initial values (Resizable depend on availability).
  • External RAM: Include "external" RAM in the core by using Block RAM (Resizable depend on availability).
  • Download:
  • Implementation Details
  • The VHDL codes are synthesized and implemented using Xilinx WebPack 3.2.
  • The synthesis and implementation tool is available for free from Xilinx web site.
  • Since the program ROM is built inside the FPGA's Block RAM, the program code for running the microcontroller should be included during implementation. This is done by specifying the program code (in binary) in UCF (user constraint file) file, which is read during implementation.
  • A utility program in the link below has been written to convert binary (*.bin) file to UCF format.
  • New!! Another utility program has been written which allows you to modify Block RAM initialization in NCD file! With this utility, you don't have to rerun place & route process, but just rerun the final bitstream file creation. It saves your time in waiting for implementation if you are not changing the design, but just changing the ROM content.
  • The core is implemented in Xilinx Spartan II FPGA (XC2S200 PQ208-5) on B3-SPARTAN2+ prototyping board.
  • Initial tests on the implementation were successful.
  • The implementation uses 1605 slices in FPGA (68% of XC2S200). Maximum clock frequency is 14.6MHz as reported by implementation tool. However, actual tests shown that the clock frequency can go as high as 48MHz in normal conditions.
  • Download 1: Bin2BlockRAM.exe (Needs MFC library files)
  • Download 2: Bin2NCD.exe (Needs MFC library files) New!!
  • 8051 C Compiler
  • Any existing 8051 compiler can be used to create program code for the core.
  • A free 8051 C compiler is available from SDCC.
  • Download link below provides the properly configured compiler (Win32 environment). It also includes a simple LED blink example, a hex to binary file converter, and a few batch files for user ease. User just need to add the bin directory to path environment.
  • To compile a program, at command prompt:
    C51 ledblink.c
  • The output is in Intel format hex file (*.ihx).
  • To convert the hex file to binary file, at command prompt:
    HB ledblink
  • Download:
  • Final Notes
  • The core is provided for free as is without any support.
  • Use it at your own risk. The author is not responsible for any consequences caused by using the core.
  • The primary purpose of this core is for academic uses including student projects and additional studying material for relevant course subjects.
  • Any suggestion and improvement on the core are welcomed.
  • Contact Info
    Koay Kah Hoe
    Faculty of Engineering and Technology
    Multimedia University (Malacca Campus), Malaysia

    Last modified : 20 June 2001