Instructor :

Dr. Chi-Ying Tsui                [Email: eetsui@ee.ust.hk; Tel.: 2358-7071; Rm.:2522]

Technican:

N/A

Teaching Assistant :

Qian zhiliang (Toby)   [Email: qianzl@ust.hk; Tel.: 2358-8844; Rm.:3114]

Time & Venue:                    
Lecture   :   Tuesday (15:00-17:50pm) Rm. 4480
Lab       : Free access all time @ Rm. 3114(A)
Office Hour : Tuesday, 1:00pm-3:00pm

Course Description:
ELEC 516 is dedicated for structured design styles; specification, synthesis and simulation using Hardware Descriptive Language (HDL); Structural chip design and system design; Circuit design of system building blocks: arithmetic unit, memory systems; clocking and performance issues in system design; Design-Automation tools and their applications.
Extensive use of CAD tools and HDL modeling-Synopsys and Cadence tools; Design project…
Prerequisite: ELEC151, ELEC301; Exclusion : EESM516

Text and Reference Books:

  Major Text:

• J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits-A Design Perspective”, 2nd Edition, Prentice Hall
• "VHDL: Analysis and Modeling of Digital Systems", by Zainalabedin Navabi, 2nd Edition

Major Reference:

• Weste and Eshraghian “Principles of CMOS VLSI Design - A System Approach” Third Edition
• Wayne Wolf, “Modern VLSI Design, System-on-chip Design”, third edition
• "Synthesis and Optimization of Digital Circuits", by Giovanni De Micheli
• "A Designer's Guide to VHDL Synthesis" by Douglas E. Ott and Thomas J. Wilderotter
• Synopsys Manual
• Cadence Design Systems documentation
• Research papers

Notice:

(New !!!)  Tutorial arrangement:

Venue :Rm 2463  , Feb 25^th (Thu ),    18:30—21:30pm

(New !!!)  Mid-term arrangement:

Venue:Rm 4480 , March 30^th (Tue) , 15:00 – 18:00pm