System-on-a-Programmable-Chip Development Board...


 


System-on-a-Programmable-Chip Development Board

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SOPC Development Board Package ±¸¼º¹°

Table 1. ±¸¼º ³»¿ë¹°
SOPC Development Board
  1. SOPC Development Board
  2. APEX DeviceÀÇ ConfigurationÀ» À§ÇÑ MasterBlaster download cable
  3. Á¦Ç° CD-ROM: ´ÙÀ½ÀÇ ³»¿ëµéÀÌ Æ÷ÇԵǾî ÀÖ½À´Ï´Ù...

Board Feature

  • Powerful development board for system-on-a-programmable-chip designs
    • Features an APEX EP20K400 device
    • Supports microprocessor intellectual property (IP)-based design
  • Industry-standard interconnects
    • 10/100 Ethernet with full and half duplexing
    • Peripheral component interconnect (PCI) mezzanine connector
    • High- and low-speed universal serial bus (USB) host supporting the Universal Serial Bus Specification, Revision 1.0
    • IEEE Std. 1394A at 100, 200, and 400 Mbits/second
    • IEEE Std. 1284 parallel interface
    • 2 RS-232 ports (DCE and DTE)
    • 2 PS/2 ports for mouse and keyboard
  • Memory subsystem
    • 2 banks of 1-Mbyte cache memory
    • 64-Mbyte SDRAM in a DIMM socket
    • 4-Mbyte FLASH memory
    • 256-Kbyte EPROM
  • Multiple clocks for communications systems design
  • Multiple debug ports
    • SignalTap embedded logic analyzer
    • IEEE Std. 1149.1 Joint Test Action Group (JTAG)
    • Extended JTAG (EJTAG)
  • Supports 50 user I/O lines
  • Additional features
    • VGA monitor interface
    • 4 user-defined switches and 6 LEDs
    • Liquid crystal display
    • Application LEDs
  • Applications
    • Embedded systems prototyping
    • Communications systems design
    • IP development and debugging

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The Altera system-on-a-programmable chip board is a development and prototyping platform that provides system designers with an economical solution to hardware verification.  Unlike other development boards, the Altera system-on-a-programmable chip board supports a variety of microprocessor-based designs by incorporating memory, debugging, and interface resources.

The board is primarily designed for implementing microprocessor functions and other standard IP functions in the on-board APEX device.  The board includes physical interfaces for widely used standard interconnects; control logic for the interconnects can be implemented in the device.

The board also supports EJTAG for development and debugging of MIPS-like microprocessor functions, as well as JTAG for other system testing.  For additional analysis, the JTAG port can be used with the SignalTap embedded logic analyzer available with the Altera Quartus development software.

Board »çÁø

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