Asia Pacific Technology Roadshow 2010
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Date: August 2010 to November 2010
Region: Asia Pacific
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Altera's Technology Roadshow will be held in China,
Korea,
Singapore,
Malaysia,
Taiwan,
and India.
You can get the complete event agenda, seminar
abstract, and registration
contacts below.
Topics
Note:
- Seminar content will vary between cities.
Event Schedule
and Registration Contacts
Korea
Date |
City |
October 6, 2010 9:00 am -
6:00 pm |
Seoul |
To register and reserve your seat, please complete the
registration form (pdf,
doc)
and then email or fax it to the local sales office or authorized
distributors. |
|
Singapore
Date |
City
|
October 12, 2010 9:00 am -
6:00 pm |
Singapore
|
To register and reserve your seat, please
complete the registration form (pdf,
doc)
and then email or fax it to the local sales office or authorized
distributors. |
|
Malaysia
Date |
City
|
October 14, 2010 9:00 am -
6:00 pm |
Penang
|
To register and reserve your seat, please
complete the registration form (pdf,
doc)
and then email or fax it to the local sales office or authorized
distributors. |
|
Taiwan
Date |
City
|
October 20, 2010 9:00 am -
6:00 pm |
Taipei
|
October 22, 2010 9:00 am - 6:00 pm |
Hsinchu
|
To register and reserve your seat, please
complete the registration form (pdf,
doc)
and then email or fax it to the local sales office or authorized
distributors. |
|
India
Date |
City
|
November 23, 2010 9:00 am -
6:00 pm |
Bangalore
|
November
26, 2010 9:00 am - 6:00
pm |
Delhi
|
To register and reserve your seat, please
complete the registration form (pdf,
doc)
and then email or fax it to the local sales office or authorized
distributors. |
|
Seminars, Topics, and Abstracts
Introducing
28-nm Stratix V FPGAs: Built for Bandwidth
While supporting increasingly demanding bandwidth requirements, your products
also need to meet stringent cost and power budgets. Altera's new 28-nm Stratix V
FPGAs deliver what you need through groundbreaking innovations such as faster
transceivers and external memory interfaces, partial reconfiguration, DSP
blocks, on-chip memory, adaptive logic modules (ALMs), and delta-sigma
fractional phase-locked loop (fPLL) capabilities.
PCI Express
Design with Altera’s Transceivers
With a simple design flow, you can easily create PCIe® designs
with Altera embedded hard IP. This presentation introduces the key features of
the PCIe hard IP embedded in Stratix, Arria®, and Cyclone®
series FPGAs.
Easily Build
Designs Using Altera’s VIP Framework
VIP designers are faced with difficult challenges such as how to improve
image format conversion quality, offload DSP tasks, reduce system cost, and
reduce time to market. Altera’s VIP framework is an ideal solution for rapidly
resolving these challenges. In this technical VIP session, you will understand
Altera’s VIP framework and VIP design approach through a live demo.
Quickly
Master SDC Timing Analysis
Timing analysis is critical for geometries of 65 nm and smaller. You need to
know how to set timing constraints easily, how to generate timing reports that
improve timing analysis productivity, and how to improve FPGA timing
performance. In this technical session you will learn how to resolve these
challenges by understanding the basics of timing analysis and the SDC-based
timing analysis approach. You will also receive other timing analysis
resources.
Using Altera
FPGAs to Implement WDR ISP and Video Analytics
A new generation of WDR sensors, coupled with the emergence of the Internet
protocol camera market, present a unique opportunity for camera makers to
introduce dramatically superior products within existing price brackets. This
new level of megapixel WDR performance finally meets customer requirements—which
have been unfulfilled for the last two decades—for image quality in all
environments.
To achieve the potential offered by this WDR sensor technology, a new
generation of ISP technology is needed, based on advanced algorithms capable of
processing the full range of real-world scenes at high pixel rates.
We will discuss the challenges faced by camera designers who intend to
achieve a high level of WDR performance and describe Altera partner Apical’s
latest ISP which is the result of a 10-year development program. Using
state-of-the-art image processing techniques, the ISP can support WDR sensors up
to 120 dB at 1080/60p while achieving broadcast-level image quality. Implemented
within low-cost FPGAs, it provides the basis for rapid development of
next-generation WDR surveillance cameras.
Flexible
Industrial Ethernet Solutions on a Single FPGA Platform
Flexible, reliable, and able to support multiple standards on the same
platform, Altera FPGAs give you the ability to create adaptable,
obsolescence-proof designs for your industrial automation and process control
products.
From programmable logic controllers (PLCs) to motion and motor controllers,
I/O modules, human machine interface (HMI) panels, and intelligent drives, you
will can reconfigure your products during development or even in the field. You
can also realize lower costs of ownership, while being more productive. In this
session, you will learn about Industrial Ethernet IP and development kit
solutions from Altera and its partners. Powerlink Association China will present
how to implement the Powerlink protocol with Altera FPGAs.
High
Precision and Efficiency—No Compromise with the Industry’s First
Variable-precision DSP Architecture
With Altera’s DSP Builder Advanced Block Set, you can dramatically reduce
your product time to market and achieve highly efficient FPGA resource
utilization with the industry’s first variable-precision DSP architecture. We
will demonstrate the new DSP block architecture and provide application
examples.
Enabling
High System Performance with Altera’s New Memory Controller IP
Timing and signaling are the critical factors in external memory design.
Altera’s new memory controller and UniPHY give you high system performance by
providing higher clock date rates, low latency, ease of use and debugging,
voltage and temperature (VT) tracking, and PLL and delayed-lock loop (DLL)
sharing. A demo will show you the design flow and how to initialize, design, and
debug a memory controller.
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