The Designer's Guide to VHDL
Peter J. Ashenden
Table of Contents
This is a list of chapters and appendices in The Designer's Guide to VHDL. Follow the links to
a more detailed listing of topics.
B The Predefined Package Standard
Detailed Table of Contents
1.1 Modeling Digital Systems
1.2 Domains and Levels of Modeling
1.4 VHDL Modeling Concepts
Mixed Structural and Behavioral Models
Analysis, Elaboration and Execution
1.5 Learning a New Language: Lexical Elements and Syntax
2 Scalar Data Types and Operations
2.1 Constants and Variables
Constant and Variable Declarations
2.4 Attributes of Scalar Types
2.5 Expressions and Operators
Summary of Loop Statements
3.5 Assertion and Report Statements
4 Composite Data Types and Operations
4.2 Unconstrained Array Types
String and Bit-String Literals
Unconstrained Array Ports
4.3 Array Operations and Referencing
5 Basic Modeling Constructs
5.3 Behavioral Descriptions
Transport and Inertial Delay Mechanisms
Concurrent Signal Assignment Statements
Concurrent Assertion Statements
Entities and Passive Processes
5.4 Structural Descriptions
Component Instantiation and Port Maps
Design Libraries, Library Clauses and Use Clauses
6 Case Study: A Pipelined Multiplier Accumulator
Testing the Behavioral Model
6.3 A Register-Transfer-Level Model
Modules in the Register-Transfer-Level Model
The Register-Transfer-Level Architecture Body
Testing the Register-Transfer-Level Model
Return Statement in a Procedure
Unconstrained Array Parameters
Summary of Procedure Parameters
7.3 Concurrent Procedure Call Statements
Pure and Impure Functions
Overloading Operator Symbols
7.6 Visibility of Declarations
8 Packages and Use Clauses
Subprograms in Package Declarations
Constants in Package Declarations
8.4 The Predefined Package Standard
9.1 Aliases for Data Objects
9.2 Aliases for Non-Data Items
10 Case Study: A Bit-Vector Arithmetic Package
10.1 The Package Interface
10.3 An ALU Using the Arithmetic Package
11.1 Basic Resolved Signals
Composite Resolved Subtypes
Summary of Resolved Subtypes
11.2 IEEE Std_Logic_1164 Resolved Subtypes
11.3 Resolved Signals and Ports
11.4 Resolved Signal Parameters
12.1 Parameterizing Behavior
12.2 Parameterizing Structure
13 Components and Configurations
13.2 Configuring Component Instances
Basic Configuration Declarations
Configuring Multiple Levels of Hierarchy
Direct Instantiation of Configured Entities
Generic and Port Maps in Configurations
Deferred Component Binding
13.3 Configuration Specifications
14.1 Generating Iterative Structures
14.2 Conditionally Generating Structures
14.3 Configuration of Generate Statements
15 Case Study: The DLX Computer System
15.1 Overview of the DLX CPU
The DLX Entity Declaration
The DLX Instruction Set Package
The DLX Behavioral Architecture Body
15.3 Testing the Behavioral Model
The Test-Bench Clock Generator
The Test-Bench Architecture Body and Configuration
15.4 A Register-Transfer-Level Model
The Arithmetic and Logic Unit
The Configuration Declaration
15.5 Testing the Register-Transfer-Level Model
16.1 Guarded Signals and Disconnection
Guarded Signal Parameters
16.2 Blocks and Guarded Signal Assignment
Disconnection Specifications
16.3 Using Blocks for Structural Modularity
Generics and Ports in Blocks
Configuring Designs with Blocks
17 Access Types and Abstract Data Types
Access Type Declarations and Allocators
Assignment and Equality of Access Values
Access Types for Records and Arrays
17.2 Linked Data Structures
Deallocation and Storage Management
17.3 Abstract Data Types Using Packages
18 Files and Input/Output
Files Declared in Subprograms
Explicit Open and Close Operations
File Parameters in Subprograms
Reading and Writing User-Defined Types
19 Case Study: Queuing Networks
19.1 Queuing Network Concepts
19.2 Queuing Network Modules
A Package for Token and Arc Types
19.3 A Queuing Network for a Disk System
20.1 Predefined Attributes
Attributes of Scalar Types
Attributes of Array Types and Objects
Attributes of Named Items
20.2 User-Defined Attributes
21.1 Buffer and Linkage Ports
21.2 Conversion Functions in Association Lists
A.2 A Synthesis Subset of VHDL
Using IEEE Standard 1164 Logic Types
A.4 The Draft P1076.3 Standard Synthesis Package
A.5 Examples-"Doing It Right"
A.6 Examples-"Doing It Wrong"
A.7 Hand-Instantiation-"Doing It the Hard Way"
B The Predefined Package Standard
D.1 IEEE Std. 1029.1: WAVES
D.2 IEEE P1076a: Shared Variables
D.3 IEEE P1076.1: VHDL-A - Analog Extensions to VHDL
D.4 IEEE P1076.2: Standard VHDL Language Mathematical Package
D.5 IEEE P1076.3: Standard VHDL Language Synthesis Package
D.6 IEEE P1076.4: Timing Methodology (VITAL)
D.7 IEEE P1076.5: VHDL Utility Library
D.8 IEEE P1165: EDIF Interoperability
D.9 EIA-567-A: Component Modeling and Interface Standard
E.2 Library Unit Declarations
E.3 Declarations and Specifications
E.5 Concurrent Statements
E.6 Sequential Statements
E.7 Interfaces and Associations
F Differences Between VHDL-87 and VHDL-93
Differences in the Standard Environment
VHDL-93 Facilities Not in VHDL-87