To be supervised by Peter Ashenden
email: petera@cs.adelaide.edu.au
phone: 8303 4477
Room 3031, Plaza Building
Several of these projects are part of the SUAVE research project. SUAVE is an extension to the VHDL hardware description language. It adds capabilities for object-oriented data modeling, generic data types and design entities, and abstract communication using message-passing channels. These facilities improve VHDL for sue in high-level design of digital and computer systems.
This project involves developing models of an MPEG decoder IC using object-oriented modelling
techniques. Models will be
developed using SUAVE, an object-oriented extension to the language VHDL. The aim of the
project is to evaluate the support
provided by the language extensions for high-level modelling and for model refinement. The
project is supported by Siemens AG,
and will involve visits to their lab in Munich for collaborative work. The project would be best
suited to a student with some engineering background.
These projects involve development of libraries of reusable parameterized hardware and software
components to support design of
VHDL hardware models and testbenches. The libraries will be written using the SUAVE
extensions to VHDL. The projects will
also involve design projects to demonstrate use of the libraries. The hardware component
library project would be best suited to a student with some engineering background. The
software component library project may be undertaken by a student without formal engineering
background, but with some informal understanding of digital systems and computer systems.
This project involves extending the SAVANT compiler and simulator to support the SUAVE language extensions. A number of subprojects are available, each involving implementation of different language features in the compiler and simulator run-time support. The work will involve collaboration with developers at Adelaide and the University of Cincinnati, USA. No hardware design background is assumed.
This project involves extending the SUAVE/SAVANT compiler to generate control/data flow graphs (CDFGs). GDFGs represent the flow of sequential control and operands between operators in a VHDL model, and are used as the basis for synthesis of hardware from a behavioural description of a system. No hardware design background is assumed.
This project will involve development of a kernel to support parallel discrete event simulation (PDES) using the Time-Warp PDES algorithm. The kernel will be developed in Java, and build on the techniques used in the Warped PDES kernel from the University of Cincinnati. The project will be undertaken in conjunction with the Distributed High Performance Computation (DHPC) group at Adelaide.