Peter Ashenden Department of Computer Science University of Adelaide, SA 5005  Australia  Email:petera@cs.adelaide.edu.au Phone: +61 8 8303 4477  Fax: +61 8 8303 4366  PGP public key (contact me for footprint)

Books

The Designer's Guide to VHDL , published by Morgan-Kaufmann Publishers, ISBN 1-55860-270-4

The Student's Guide to VHDL , published by Morgan-Kaufmann Publishers, ISBN 1-55860-520-7

Current Research Projects

These are projects that I am currently supervising.

SUAVE: SAVANT and University of Adelaide VHDL Extensions

High-Level Synthesis for Asynchronous Digital Systems (PhD project, Sue Tyerman)

Proposed  Research Projects

These are projects that I am seeking students to work on.

Honours Projects for 1999

SUAVE/MPEG - in collaboration with Siemens AG, Munich, Germany (M.Eng. Sc. project)

• with potential to follow on to work on evaluating object-oriented modeling methology for hardware design (PhD project)

SAUVE/SID - System-Level and Interface Description Languages (PhD project)

Modeling and Synthesis of Analog/Mixed-Signal Systems (PhD project)

SUAVE Hardware and Software Component Libraries (Final Year Engineering project)

Information about me - Professional

Follow this link to see my full curriculum vitae and publication list.

I am a Senior Lecturer in the Department of Computer Science at the The University of Adelaide. I graduated with B.Sc.(Hons) from this department in 1982, and joined the Leopard Multiprocessor Project at its inception as a Research Officer. I was responsible for system architecture, project management, and some detailed engineering design. The project group designed and constructed a series of multiprocessor workstation prototypes, with research emphasis on the shared memory, coherent cache architecture. Whilst working in the Project, I undertook a part time doctoral program, investigating cache coherence protocols for shared memory multiprocessors.  My doctoral degree was conferred in 1997.

In July 1990, I joined the academic staff of the department as a Lecturer. I have concentrated on teaching computer systems and computer architecture, but have also taught programming and data structures subjects.

My current research interests are computer modeling using hardware description languages (especially VHDL), parallel discrete event simulation for HDLs, and graphical representation of designs usign HDL semantics. I spent 1997 on sabbatical in the Department of ECECS at the University of Cincinnati, working on SUAVE: extensions to VHDL to improve high-level modeling. I am continuing that work here at Adelaide.

I have published a number of research papers, and a booklet called The VHDL Cookbook. Some of this work is available for ftp. I have also written two text books,  The Designer's Guide to VHDL and  The Student's Guide to VHDL, published by Morgan-Kaufmann Publishers.