VLIW Abstract Machine

Fe t ch

Instruction Memory

address

Ipacket_vec

Register File

Read Request Port

Read Result Port

Write Port

Execute Unit(s)

In Port

Out Port

Epacket_vec

Mpacket_vec

Mem Unit

Data Memory

address

RF Write Unit

Wpacket_vec

mem read data

mem write data

Rpacket_vec

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