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Subject: Re: fastest 32 bit RISC
Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl
Date: Thu, 13 Jan 2000 16:17:50 -0800

>Ulf Samuelsson wrote:
>> I doubt that you can get 50 Mhz with an FPGA implementation.
>> If you are lucky You might get  10-15 Mhz in very advanced technology.
...
>> ... Also they will be quite expensive. ...

Ray Andraka wrote in message <387DE9AE.7678F6F@ids.net>...
>...  Jan Gray can probably give you some real bench marks.  ...

For starters, Philip Freidin's 16-bit RISC4005 was built with advanced 1990
technology. :-)

The 32-bit J32 (1995) (www3.sympatico.ca/jsgray/homebrew.htm) fit in 60% of
an XC4010-5 and did 16 MIPS at 33 MHz.

My newer small-footprint 16-bit RISC fills 70% of an XC4005XL/XCS10XL and
has a 28 ns cycle time in an 'S10XL-4 (says trce), and that includes several
ns of delays outside the CPU core.  A similar 32-bit version has a 34 ns
cycle time in 60% of an 'S20XL-4.  These results are for the slowest speed
grades of SpartanXLs, which are among the least costly FPGAs sold.  A port
to Spartan2 will be much faster, and cost perhaps a dollar's worth of area.

One key to speed/area performance is selecting a simple instruction set that
is a good match for the FPGA architecture.  (A 32-bit barrel shifter is a
large fraction of the size of a compact 32-bit core, and is rarely
cost-effective when you can build fixed 1-bit, 4-bit, etc. shifters in 0
CLBs (using TBUFs).)

If pure speed (not area) is the goal, then using dual port selectRAM for the
register file, logic (not TBUFs) for the result mux, and assuming a MEM pipe
stage, the processor cycle time can be approximately the max of:

1. time to read the register file operands (time from latching the
instruction) and to write back a result,
2. time for operand register clock-to-out + adder delay + result mux delay +
result forwarding mux delay + operand register setup,
3. time from address register clock-to-out + selectRAM/blockRAM read + max
(result mux delay + etc, tag check).

which for a floorplanned Virtex datapath is not very many ns.

I note the 100 MHz result posting from Damjan Lampret and the opencores.org
folks.  Nice work.  Synthesized even!  Do you floorplan?

Jan Gray
Gray Research LLC

Subject: Re: fastest 32 bit RISC
Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl
Date: Thu, 13 Jan 2000 22:37:24 -0800

>> I note the 100 MHz result posting from Damjan Lampret and the
>opencores.org
>> folks.  Nice work.  Synthesized even!  Do you floorplan?
>
>No floorplanning.

Incredible.  In addition to your (I assume) excellent work, I see now that
synthesis tools and the automatic P&R tools are more improved, and Virtex is
even faster, than I had realized.  Please tell us about your tools when
appropriate.

I have the eerie tingly feeling that we have turned the corner into a new
era -- a realization (for me) which couldn't have come in a more appropriate
month.

Fellas, perhaps it's time to set down our FMAPs and RLOCs and RPMs and
XC4000s and move along.  It's been fun.

Jan Gray
Gray Research LLC