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Subject: Re: Minimal ALU instruction set. Date: 19 May 1998 00:00:00 GMT Newsgroups: comp.arch,comp.arch.fpga,comp.arch.embedded Peter wrote in message <3561443d.214920709@news.netcomuk.co.uk>... > >I may have missed the original post, but may I ask why anyone wants to >do this project? Is it just an exercise? > >Many people have thought about doing a CPU in an FPGA, but AFAIK it is >always a futile exercise because one can buy a CPU with a given >capability for far less than the cost of the FPGA. You're right. But what fun! I used to envy processor designers in industry and academia. Now I can do my own processors, on-chip peripherals, cache, etc. In fact, I have it far better. I can design the entire system, the ISA, the microarchitecture, and get working hardware in a few days. In contrast, the typical big company CPU designer works for months at a stretch on a small piece of a huge and complex system. And there is a certain pleasure in minimalism and self-sufficiency. It is one thing to read about simple microarchitectures in H&P, it is another to go build and debug and boot them. You can "squish the CLBs between your toes" -- you become familiar with the same pipe stages, clock speed, area, IPC tradeoffs, although your units are CLBs and ns rather than rbes and ps. The resulting designs are only as fast as seven year old commodity processors, but that's OK. Maybe 20X a VAX is fast enough for your application -- you don't need 200X a VAX. And whether you have a StrongARM, an R4640, or a custom FPGA CPU, you are using the same external memory, more or less -- cache misses still cost 100 ns. True, commodity processors are cheaper on an absolute basis, especially if you don't take into account total system cost. But FPGA prices are coming down. By end of 1998, the Xilinx XCS20 will be $6.50 Q100K (ref: http://www.xilinx.com/prs_rls/spartan.htm). This part, equivalent to the XC4010 that hosts the J32 (1995), can implement a 33 MHz conventional pipelined 32-bit RISC processor leaving 5,000 gates of logic for system-on-chip peripherals. You will soon be able to build highly integrated and customized glueless systems with just FPGA+SDRAM for ~$10. And there is the soon-to-be-$3 XCS05, adequate for a nice little 10 MIPS 16-bit processor with logic to spare. Implications/Predictions (some from other folks) * falling FPGA prices will eventually clamp an upper bound on the price of many custom parts, including embedded CPUs * RISC CPU design is no longer rocket science -- HDLs, tools, and the FPGA's abstraction of all the hard EE, means that undergrads will increasingly design their own processors. Of course, these designs will never complete with commodity microprocessors for specmarks. * a number of these designs will be published under GPL or put in the public domain. There will be communities of users of certain free CPU designs, similar to the open software movement. There will be GCC tools chains, lunatic fringe Linux ports, etc. * there will be free implementations of legacy ISAs. Or perhaps free implementations of cross-assemblers/cross-loaders from legacy ISAs to simplified minimalist FPGA CPU ISAs. * embedded CPU vendors will start to ship with some FPGA on chip (Motorola and Atmel have announced this). Jan Gray (J32 described at http://www3.sympatico.ca/jsgray/homebrew.htm)
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