This page shows
the progress of Verilog FAQ through different versions.
Version
09/15: 09/15/2005 This is the current version.
- Verilog history
updated to include links to System Verilog
-
Conferences
and Paper contests section
updated.
- Website links cleaned up.
-
Link
to ISD magazine archives and Chip design magazine added.
Version
10.03: 09/29/2003
- Conference
Proceedings archive section added in Part
1
-
GPL
CVer added in Free Verilog Tools
section in added in Part
1.
- Links to two free
Wave form viewers for Icarus added in Part
1.
-
Free
Verilog Code coverage tool section
added in Part
1
- Free
Verilog Obfuscator added in Part
1
- Magma's Blast Create added in Synthesis
tools in Part 2
Version
10.02: 11/06/2002
- Verilog to
C/C++/SystemC Converter
list updated in Part 3.
- Free
Verilog to C++ / System C Translator
added in Part
1.
- Conferences and
Paper contests
updated in Part 1.
- A new section on "Connecting
other scripting languages to Verilog" added in Part2
- Books
and Reference material on Verilog in Part 1 updated
with J.M. Lee's book.
- A new section on VCD
(Value Change Data) added in technical section of FAQ Part
2.
Version
10.01:
10/11/2002
- Surendra Anubolu's
ASICDesign Info page added on Links
page.
- Online simulator added in free
simulators page.
- Verilog BNF link added to Part 1.
- Technical question on
compiling files from Emacs added in Techical QA
page.
Version
10.00:
03/21/2002
- Obsolete links removed. many
links cleaned up.
- Ben Cohen's new book added
in list
of Verilog Books.
- CVer of Pragmatic-C added in
the list
of free Verilog Simulators.
Version
9.13: 06/09/2001
-
Many web sites added in "Participating
in discussions on comp.lang.verilog" in Part 1.
-
Google Search Engine Added.
-
Source Navigator for Verilog added in
"Editors
which support Verilog" section in Part 1.
-
Icarus, Ver, VBS and old
Veriwell (Linux) simulators added in the list of "Free
Verilog Simulators" in Part 1.
-
Link to "Micron Memory Models" in Part
3 corrected.
-
Comit System's Reference card
added in "Free Verilog quick reference card" in Part 1.
-
CynApps product Cynchronizer added in
"Verilog
to C Converters" in Part 3.
-
CynApps product Cynthesizer added in
"C/C++
to Verilog Converters" in Part 3.
Version
9.12: 04/07/2001
-
Dolphin Integration's SMASH simulator
added in the list of
simulators in Part-3.
-
Free Timing Analyser added in Free
Stuff section in Part1.
-
Free VHDL to Verilog Translator added in
Free
Stuff in Part1.
-
Usenet Information updated in Part1.
-
Conferences and Paper
contests updated
in Part1.
-
Simpod added in the list of commercial
model providers in Part3
Version
9.11: 01/01/2001
-
Main site moved to http://www.bawankule.com/verilogfaq
-
All broken links fixed.
-
nLint from Novas added to Lint
tools in Part 3.
-
javapli added in PLI
section in Part 2.
Version
9.10:
10/26/2000
-
"Conferences and Paper contests"
section in Part 1
updated.
-
"Future
of Verilog" section in part 2 updated with examples of
Verilog-AMS.
-
"Verilog
to C converter" added in Part 3.
-
Many outdated links fixed in
FAQ.
Version
9.9:
05/19/00
-
"Future of Verilog" section in Part 2 updated. Stuart
Sutherland's paper on Verilog-2000 added.
-
"Books on HDL Verification" section in Part 1 updated. Principles
of Verifiable RTL Design by Lionel Bening and Harry Foster
added.
-
"Programming Language Interface"
section in Part 2 updated.
Stuart Sutherlands book added in the list.
-
"Good Books on Synthesis" section updated with images and
correct prices.
Version
9.8:
02/23/00
-
"Conferences
and Paper contests " section added in Part 1 updated.
-
VCD Waveform viewer added in "Free
Simulation Waveform Viewer" section in part 1.
-
A new section "Free
Verilog Design Rule Checker" added in part 1.
-
A new "Free
Verilog LRM" section added in part 1.
-
On-line Verilog HDL Quick Reference
Guide by Stuart Sutherland added in "Free
Verilog quick reference card" section in Part 1.
-
"Verilog
Static Checking Tools" section in part 3 updated with
Surelint, ReviewVer and Spyglass tools.
Version
9.7:
01/25/00 This is the current
version.
-
"Books on HDL Verification" section
added in Part 1. Janick Bergeron's Book added in the
section.
-
FTL Systems added in
"VHDL to Verilog converters" section in Part 3.
Version 9.6:
12/10/99
-
"Editors
which support Verilog " section in Part1 is updated with Prism
Editor.
-
"Verilog
Code Coverage Tools" section is added in Part 3.
-
Link to Asynchronous Logic page added
in Links
page.
Version 9.5:
11/12/99
-
"Verilog
to HTML converter" section in Part1 is updated with changed
link.
-
A new section "Synthesis
Standards Working group working on Synthesis" is added in Part
2.
Version
9.4:
10/15/99 This is the current
version.
-
A new "Technical
Questions" section in Part2. A separate page is created for
these questions and answers.
-
How to model large amount of memory
without using too much simulation memory space?
-
How to model Transport and Inertial
Delays in Verilog?
-
How to display the system date in
$display or $write?
-
How to display bold
characters?
-
A new "Visual
Verilog tools " section added in Part3.
-
Prof. Don Thomas's slides on Verilog
added in "Free
Verilog Tutorials" section in Part1.
-
Michael D. Ciletti's
book added in "Books
and Reference material on Verilog" in part1.
-
Link to
HierAssist tool added in "Editors
which support Verilog" section in part1.
Version 9.3:
09/15/99
-
"Conferences
and Paper Contest" section in Part1 is
updated.
-
"Free
Verilog Tutorials" section in Part1 is
updated.
-
"Synthesis
Tools" section added in Part2.
-
"Simulators"
Section updated with InnoLogic System's ESP Symbolic
Simulator.
-
A new Search engine added on FAQ main
page.
Version 9.2:
08/15/99
-
Information on Superlog added in
"Future
of Verilog" section.
-
A new section on "Timing
Diagram Designers" added.
-
A new section "Editors
which support Verilog" added.
-
A new section on "Verilog
Static Checking Tools" added.
-
A new subsection on "Usenet
group related to synthesis" added.
Version 9.1:
07/18/99
-
Bob Zeidman's "Verilog
Designer's Library" added to list
of books.
-
Lycos's usenet site added in the
list.
Version 9.0:
06/06/99
-
C to verilog Converter added.
-
Micron memory simulation models
added in Verilog Model
examples.
-
A new section on Synthesis
added.
-
Programming Language Interface section is
updated. Information on
Swapnajit Mittra's book is added.
-
EDA Industry Working Groups added.
-
3 new links added in Verilog / EDA
Links Page
Version
8.3:
05/12/99
-
Links checked and
corrected.
-
Links to PDF documents
changed.
Version 8.2:
03/04/99 New items
-
Examples from "The Verilog Hardware
Description Language" by
D.E. Thomas and P.R. Moorby are added.
-
Verilog / EDA Benchmarks are
added.
Version 8.1:
01/14/99 Updated items
-
SynpatiCAD's VeriLogger added in
Free and commercial simulators list.
-
SynpatiCAD's Waveformer Pro
added in free and commercial waveform viewer
list.
-
Links for VCS
updated.
Version 8: 12/15/98 New
Items
-
List of two free verilog
tutorials added.
-
List of Verilog / EDA related
conferences added.
-
FSM Design and Analysis tools
section added. Links to Cisco FSM and FSM Designer
added.
Updated items
-
FAQ page moved to Angelfire
site. HTML is cleaned up.
-
Information on SMASH mixed
signal simulator added.
-
Information on J. Bhasker's
"Verilog HDL Synthesis, A Practical Primer" added in list of
books.
-
Qualis quick reference card
added in the list of free cards.
-
Links for Analog Verilog and PLI
updated.
Version 7:
08/01/1998
-
Thorough change in look and feel
of web pages.
-
Breakup of one single FAQ page
into logical three pages.
-
Reorganization of information in
three sections.
-
"What's New" page is added to
indicate version history.
-
Verilog parser contributed by
Coy Toavs added.
-
Link to Veripool (public domain
Verilog resources) added.
-
Examples of simple Verilog
models added in technical section.
-
Links to various companies
providing Verilog models added in Tools and services
section.
Version 6.1
04/27/1998
-
Information about Verilog-AMS
(Analog and Mixed Signal) added
-
Information about free PC
simulators modified.
Version 6.0 04/11/1998
-
Links to Verilog Emacs mode is
modified.
-
Information on Verilog text file
to HTML conversion is added.
Version 5.0 10/26/1997
-
Link to Verilog mode for Emacs
added.
-
Fix for printing Rajeev
Madhavan's Verilog quick reference card added.
-
Comit System's Verilog quick
reference card added.
-
Link to EDN in EDA related
magazines added.
-
Avanti's name in Simulator
companies list added.
-
Absolete comparisons between
simulators removed.
Version 4.0 07/01/1997
New Items
-
Verilog Preprocessor
link
-
Efficient State machine
design
Updated items
-
PLI : Swapnajit Mittra's
site added.
-
Books : James Lee's book
added in the list.
Version 3.0 06/04/1997
-
A new "Technical Topics"
section. This time information about state machine design is
added.
-
Book section is modified. J.
Bhasker's new book is added in the list.
Version 2.0 03/30/1997
It contains major additions of topics
like
-
List of companies making Verilog
simulators.
-
Different types of
simulators
-
VHDL to Verilog
converter
Following topics are updated.
-
PLI
-
Related web
sites
Version 1.0 02/27/1997
-
The first version released based
on old FAQ. |