EE 8993 VLSI Systems I

This is the home page for VLSI Systems I (also known as VLSI II) course for the Fall '98 semester. 'Intro to VLSI Design' (VLSI I, EE4253) is a prerequisite for this course. The object of this course is to discuss system aspects of VLSI design; as such we will be concentrating on the design of larger blocks such as RAMS and datapaths. We will also look at the use of tools such as macro cell place/route and cell tilers.

Textbook

I will use the textbook used in EE 4253 (Principles of CMOS VLSI Design , Weste) and Digital Integrated Circuits , Rabaey.

Skills

1. The Cadence tool suite will be used this semester. This is the first semester that we have used it, so I imagine things will go somewhat rough. We will use the basic layout editor, the standard cell place and route (Silicon Ensemble), and the layout generator (LAS).
2. I also expect students to be able to write/read Perl scripts. If you need a Perl manual, please see me.

Policy

The grading policy will be:

• 50% Tests (3 tests)
• 10% Final
• 40% External Assignments

All external assignments are to be INDIVIDUAL work. You may discuss the assignments with other students but you may not share any work, or show anybody your work as examples of how to do something. Any violations of this policy will result in the assignment of a failing grade for the ENTIRE course.

Links to Course Information

• Lecture 1 -- Interconnect
• Lecture 2 -- Standard Cell Routing
• Lecture 3 -- Standard Cell Library assignments
• Lecture 4 -- Delay Optimization - Part I
• Interesting note on Copper wire use

Assignments

• Delay Optimization
• Dynamic Logic