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Access Type
Aggregate
Alias
Allocator
Architecture
Array
Assertion Statement
Attributes (predefined)
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Bit
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Block Statement
Boolean
Case Statement
Character Type
Component Declaration
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File Declaration
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Generate Statement
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If Statement
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Name
Next Statement
Null Statement
Operator Overloading
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Physical Type
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Process Statement
Range
Record Type
Report Statement
Reserved Word
Resolution Function
Resume
Return Statement
Scalar Type
Sensitivity List
Signal Assignment
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Slice
Standard Package
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Std_Logic_1164 Package
Std_Logic_Vector
String
Subtype
Suspend
Testbench
Type
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Use Clause
Variable Assignment
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VITAL
Wait Statement
Waveform

Report Statement

Formal Definition

A statement that displays a message.

Simplified Syntax

report string;

report string severity severity_level;

Description

The report statement is very much similar to assertion statement. The main difference is that the message is displayed unconditionally. Its main purpose is to help in the debugging process.

The expression specified in the report clause must be of predefined type STRING, and it is a message that will be reported when the assertion violation occurred.

If the severity clause is present, it must specify an expression of predefined type SEVERITY_LEVEL, which determines the severity level of the assertion violation. The SEVERITY_LEVEL type is specified in the STANDARD package and contains following values: NOTE, WARNING, ERROR, and FAILURE. If the severity clause is omitted in a report statement it is implicitly assumed to be NOTE (unlike in an assertion statement, where the default is ERROR).

Examples

Example 1

while counter <= 100 loop
  if counter > 50
    then report "the counter is over 50";
  end if;
  . . .
end loop;

 
Whatever happens inside the loop, if the value of counter is greater than 50 it will be reported by the listed message. The severity clause is omitted here because the selected level is the same as the default one (NOTE).

Important Notes

  • The report statement was introduced as late as in VHDL 93 and is equivalent to the assert false statement. The latter form was the only acceptable in VHDL 87.

 

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