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Table of Contents
Access Type
Aggregate
Alias
Allocator
Architecture
Array
Assertion Statement
Attributes (predefined)
Attributes (user-defined)
Bit
Bit_Vector
Block Statement
Boolean
Case Statement
Character Type
Component Declaration
Component Instantiation
Composite Type
Concatenation
Configuration Declaration
Configuration Specification
Constant
Delay
Driver
Entity
Enumeration Type
Event
Exit Statement
Expression
File Declaration
File Type
Floating Point Type
Function
Generate Statement
Generic
Group
Guard
Identifier
If Statement
Integer Type
Library Clause
Literal
Loop Statement
Name
Next Statement
Null Statement
Operator Overloading
Operators
Package
Package Body
Physical Type
Port
Procedure
Process Statement
Range
Record Type
Report Statement
Reserved Word
Resolution Function
Resume
Return Statement
Scalar Type
Sensitivity List
Signal Assignment
Signal Declaration
Slice
Standard Package
Std_Logic
Std_Logic_1164 Package
Std_Logic_Vector
String
Subtype
Suspend
Testbench
Type
Type Conversion
Use Clause
Variable Assignment
Variable Declaration
Vector
VITAL
Wait Statement
Waveform

Std_Logic_1164 Package

Definition:

Package Std_Logic_1164 is NOT a part of the VHDL Standard Definition. It is defined as IEEE Std 1164.

Description

The Std_Logic_1164 Package contains definitions of types, subtypes, and functions, which extend the VHDL into a multi-value logic. It is not a part of the VHDL Standard, but it is a separate Standard of the same standardization body (Institute of Electrical and Electronics Engineers, IEEE).

Main reason for development and standardization of Std_Logic_1164 was the need for more logical values (than the two defined by the type Bit in the Standard package) with resolution function. The types Std_Logic and Std_Logic_Vector (declared in Std_Logic_1164 package) became de facto industrial standards.

Contents:

The package contains the following declarations:

  • type std_ulogic: unresolved logic type of 9 values;

  • type std_ulogic_vector: vector of std_ulogic;

  • function resolved resolving a std_ulogic_vector into std_ulogic;

  • subtype std_logic as a resolved version of std_ulogic;

  • type std_logic_vector: vector of std_logic;

  • subtypes X01, X01Z, UX01, UX01Z: subtypes of resolved std_ulogic containing the values listed in the names of subtypes (i.e. UX01 contains values 'U', 'X', '0', and '1', etc.);

  • logical functions for std_logic, std_ulogic, std_logic_vector and std_ulogic_vector;

  • conversion functions between std_ulogic and bit, std_ulogic and bit_vector, std_logic_vector and bit_vector and vice-versa;

  • functions rising_edge and falling_edge for edge detection of signals.

  • x-value detection functions, is_x, which detect values 'U', 'X', 'Z', 'W', '-' in the actual parameter.

See std_logic and std_logic_vector for details.

Important Notes

  • The Std_Logic_1164 Package is copyrighted and may not be altered (either by modifying/removing existing declarations or adding new ones).

  • In order to use any of the declarations of the Std_Logic_1164 package, the 'library' and 'use' clauses have to be used:

    library IEEE;

    use IEEE.Std_Logic_1164.all;

 

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